1. Field of the Invention
The present invention relates to methods of making semiconductor memory devices and memory cells for such devices, and more particularly to methods of making dynamic type semiconductor memory devices such as dynamic random access memory devices and memory cells for such devices.
2. Description of the Prior Art
Dynamic random access memory (DRAM) cells are widely used for memory elements, since they can be integrated in a highly dense manner. As is well-known, such DRAMs have only one capacitor and one switching transistor connected with the capacitor in each memory cell.
However, the degree of integration of DRAMs has recently quadrupled every three years and this tendency seems to be continuing. Although the memory capacity increases four times, the chip size increases only about two times by virtue of highly sophisticated processing technology.
However, the capacitance of a capacitor in a memory cell, which is a location for storing information in the form of millions of electrons, cannot be reduced with subsequent generations due to the operational characteristics of DRAM circuits. Most currently commercial products should be designed to have a capacitance value of about 20 femto Farad or larger per cell. In order to reduce the area per cell and yet maintain the capacitance of the capacitor, most commercial DRAMs having the integration degree of 4-mega-bits or greater use three-dimensional capacitors.
A conventional structure of a DRAM device including a three-dimensional capacitor will be now described in conjunction with FIG. 1.
In accordance with a conventional method, active and field regions are defined in P type semiconductor substrate 1. The definition of these regions is achieved by implanting channel stop ions into a desired portion of semiconductor substrate 1 to grow partially a field region, which is denoted by the reference numeral "2" in FIG. 1.
Over semiconductor substrate 1 are deposited gate insulating film 3a, polysilicon film 3b for a gate and gate cap insulating film 3c, in this order. By photo and dry etching processes, gate electrodes 3b are then formed on the active region and field region 2, respectively, as indicated. Thereafter, low concentration N type (N.sup.- type) ions are implanted in P type semiconductor substrate 1, so as to form low concentration source and drain regions
Over the resultant entire exposed surface, an insulating film is deposited which is, in turn, subjected to patterning for forming gate side walls 4. Subsequently, high concentration N type (N.sup.+ type) ions are implanted in side walls 4 so that source and drain regions with a lightly doped drain (LDD) structure are formed.
Over the resultant entire exposed surface, another insulating film is deposited which is, in turn, subjected to photo and etching processes and steps to form a buried contact and a storage node electrode as indicated. Over the storage node electrode, which is denoted by the reference numeral "6" in FIG. 1, are deposited capacitor dielectric film 7 and plate electrode 8, in this order. Capacitor dielectric film 7 and plate electrode 8 are then subjected to photo and etching processes so that their unnecessary portions are removed for producing a capacitor.
Over the resultant entire exposed surface, thereafter, insulating film 9 is deposited. Insulating film 9 is then subjected to photo and etching processes to form a bit line contact. Subsequently, bit line 10 is deposited over the resultant entire exposed surface.
The characteristic of the above-described structure is that a capacitor is provided even over a word line, thereby resulting in an increase in the capacitor surface area.
As mentioned above, the area occupied by each DRAM cell is gradually reduced in subsequent generation devices, resulting in a great reduction in the amount of electric charge to be stored in each capacitor. As a result, the content of some of the DRAM cells may be erroneously read. In this regard, it is required to provide a method of making a stacked capacitor capable of increasing the capacitor surface area. U.S. Pat. No. 4,970,564 (issued to Hitachi Ltd. in Japan) discloses a semiconductor memory device having three-dimensional stacked capacitor cells capable of increasing the capacitor surface area without increasing the capacitor height.
The method disclosed in U.S. Pat. No. 4,970,564 will now be described in conjunction with FIGS. 2a to 2i.
In accordance with this method, well 12 of a predetermined conductivity type (in a complementary metal oxide semiconductor or "CMOS" device, P type well and N type well) is first formed on silicon substrate 11, as shown in FIG. 2a. Active regions 13 and field regions 14 are then formed on silicon substrate 11 by using the improved LOCOS (local oxidation of silicon) method. Thereafter, gate insulating film 15 is formed on active regions 13.
As illustrated in FIG. 2b, word lines 16 and insulating films 17 for insulating adjacent layers from each other are then formed on gate insulating film 15 by using a well-known low pressure chemical vapor deposition (LPCVD) method and a well-known anisotropic dry etching method. Over the entire exposed surface of silicon substrate 11, insulating film 18 is then formed by using a chemical vapor deposition (CVD) method. First contact hole 30 is formed in insulation film 18 above first impurity diffusion region 19, which is located in an active region of a switching transistor such as is present in memory cells and will be electrically connected to a bit line, as illustrated in FIG. 2c. Thereafter, bit lines 20 and insulating film 21 are formed using LPCVD and dry etching methods, as illustrated in FIG. 2d. Bit line 20 is isolated from a layer which will be subsequently formed thereon, by using a conventional method forming side wall insulating film 22, as shown in FIG. 2e. Thereafter, another insulating film 23 is formed. In insulating film 23, second contact holes 29 are formed above each second impurity diffusion region 24, which is located in active region 13 of a switching transistor such as is present in every memory cell and will be electrically connected to a stacked capacitor, as illustrated in FIG. 2f. Storage electrode 25 is then formed by using LPCVD and dry etching methods, as shown in FIG. 2g. Storage electrode 25 is one of two electrodes of the stacked capacitor and will be connected to second impurity diffusion regions 24. Thereafter, dielectric film 26 for the stacked capacitor is formed.
As shown in FIG. 2h, plate electrode 27 of the stacked capacitor is then formed by using LPCVD and dry etching methods. Another insulating film 28 also is formed using a CVD method, as shown in FIG. 2i. Insulating film 28 functions to electrically insulate the stacked capacitor from metal wiring that will be formed thereon. Although not shown, additional contact holes are to be formed at proper positions. Also, metal wiring for connecting circuits are covered over the stacked capacitors by using sputtering or CVD methods and then defined by using an anisotropic dry etching method.
This DRAM cell having the above-mentioned structure of a stacked capacitor is very advantageous in extending the area of the capacitor in that the storage node electrode of the stacked capacitor can be positioned even above the contact hole connecting the bit line and a diffusion region of the switching transistor because the stacked capacitor is formed after the formation of bit lines as well as the formation of word lines, that is, gate electrodes. Accordingly, the memory cell having the improved structure of stacked capacitors can be advantageously used in DRAMs having a high degree of integration.
However, DRAM cells having the above-mentioned conventional structures having the following problems.
First, in the case of a DRAM cell having the stack capacitor structure shown in FIG. 1, the capacitor surface area can be increased by increasing the capacitor height. However, such an increase in the capacitor height has a limitation, namely because increasing the capacitor height tends to make the manufacture difficult. Furthermore, since the second impurity diffusion region, which is the junction region between the word line and the capacitor, is arranged horizontally in parallel to the first impurity diffusion region, which is the junction region between the bit line and the capacitor, it is impossible to obtain a sufficient capacitor surface area within the area per DRAM cell, which area again is limited by the desired high integration degree of the DRAM device.
Second, in case of a DRAM cell having a stack capacitor structure as shown in FIG. 2, there is an advantage that the capacitor surface area can be increased without an increase in capacitor height, as compared with the DRAM cell of FIG. 1. This is because a capacitor is laid even above the junction region of each bit line. With the DRAM structure of FIG. 2, however, the junction region between the word line and the capacitor is still arranged horizontally in parallel to the junction region between the bit line and the capacitor, as with the DRAM structure of FIG. 1. As a result, it is impossible to obtain a sufficient capacitor surface area within the area per DRAM cell, which area is limited by the desired high integration degree of the DRAM device. The DRAM structure of FIG. 2 also has the disadvantage in that the stack capacitor structure tends to make the manufacture difficult.